M2N1G64TUH8G5F / M2S1G64TUH8G4F / M2N2G64TU8HG5B / M2N2G64TU8HG4B
1GB: 128M x 64 / 2GB: 256M x 64
PC2-5300 / PC2-6400
Unbuffered DDR2 SO-DIMM
REV 1.0 4
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Input/Output Functional Description
The positive line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the rising edge
of their associated clocks.
The negative line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue.
When sampled at the positive rising edge of the clock, , , define the operation to be
executed by the SDRAM.
Reference voltage for SSTL-18 inputs
On-Die Termination control signals
Selects which SDRAM bank is to be active.
A0 – A9
A10/AP
A11, A12/A13
During a Bank Activate command cycle, A0-A12/A13 define the row address (RA0-RA12/RA13)
when sampled at the rising clock edge. A13 applies on 2GB SODIMM only.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when
sampled at the rising clock edge. In addition to the column address, AP is used to invoke
Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge
is selected and BA0/BA1/BA2 define the bank to be precharged. If AP is low, autoprecharge is
disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1/BA2 to control
which bank(s) to precharge. If AP is high all 8 banks will be precharged regardless of the state of
BA0/BA1/BA2. If AP is low, then BA0/BA1/BA2 are used to define which bank to pre-charge.
Data and Check Bit Input/Output pins.
Power and ground for the DDR2 SDRAM input buffers and core logic
Negative
and
Positive
Edge
Data strobe for input and output data
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high. In
Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not
used on x64 modules.
Address inputs. Connected to either VDD or VSS on the system board to configure the Serial
Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to V DD to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to V DD to act as a pull-up.
Serial EEPROM positive power supply.
(33 strony)
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